Modify the VHDL file to simulate a pipelined RISC CPU
Everything you need should be in the zip or linked on the site. The JPG on the site is one usable design. Again, this should be very easy if you’re at all familiar with computer architecture.
product description including more links is at this link:
And as an HTML file in the zip, Be VERY careful with this. There are similar projects from previous years on the web that look almost identical, but give completely different outputs because of subtle changes. Also the end result MUST be a VHDL file. This should be obvious since I’m asking you to make changes to a VHDL file.